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? 2003 microchip technology inc. ds21073j-page 1 24aa65/24lc65/24c65 device selection table features ? voltage operating range: 1.8v to 6.0v - peak write current 3 ma at 6.0v - maximum read current 150 a at 6.0v - standby current 1 a typical industry standard two-wire bus protocol i 2 c? compatible 8-byte page, or byte modes available 2 ms typical write cycle time, byte or page 64-byte input cache for fast write loads up to 8 devices may be connected to the same bus for up to 512k bits total memory including 100 khz (1.8v vcc < 4.5v) and 400 khz (4.5v v cc 6.0v) compatibility programmable block security options programmable endurance options schmitt trigger, filtered inputs for noise suppression output slope control to eliminate ground bounce self-timed erase and write cycles power-on/off data protection circuitry endurance: - 10,000,000 e/w cycles for a high endurance block - 1,000,000 e/w cycles for a standard endurance block electrostatic discharge protection > 4000v data retention > 200 years 8-pin pdip/soic packages temperature ranges description the microchip technology inc. 24aa65/24lc65/ 24c65 (24xx65)* is a ?smart? 8k x 8 serial electrically erasable prom. this device has been developed for advanced, low-power applications such as personal communications, and provides the systems designer with flexibility through the use of many new user-pro- grammable features. the 24xx65 offers a relocatable 4k bit block of ultra-high-endurance memory for data that changes frequently. the remainder of the array, or 60k bits, is rated at 1,000,000 erase/write (e/w) cycles ensured. the 24xx65 features an input cache for fast write loads with a capacity of eight pages, or 64 bytes. this device also features programmable security options for e/w protection of critical data and/or code of up to fifteen 4k blocks. functional address lines allow the connection of up to eight 24xx65's on the same bus for up to 512k bits contiguous eeprom memory. advanced cmos technology makes this device ideal for low-power nonvolatile code and data applications. the 24xx65 is available in the standard 8-pin plastic dip and 8-pin surface mount soic package. package types part number v cc range page size temp. ranges packages 24aa65 1.8-6.0v 64 bytes c p, sm 24lc65 2.5-6.0v 64 bytes c, i p, sm 24c65 4.5-6.0v 64 bytes c, i, e p, sm - commercial (c): 0c to +70c - industrial (i) -40c to +85c - automotive (e) -40c to +125c 24xx65 a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc nc scl sda 24xx65 a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc nc scl sda pdip soic 64k i 2 c ? smart serial ? eeprom *24xx65 is used in this document as a generic part number for the 24aa65/24lc65/24c65 devices.
24aa65/24lc65/24c65 ds21073j-page 2 ? 2003 microchip technology inc. block diagram pin function table hv generator eeprom array page latches ydec xdec sense amp. r/w control memory control logic i/o control logic sda scl v cc v ss i/o a2 a1 a0 cache name function a0, a1, a2 user configurable chip selects v ss ground sda serial address/data/i/o scl serial clock v cc +1.8v to 6.0v power supply nc no internal connection
? 2003 microchip technology inc. ds21073j-page 3 24aa65/24lc65/24c65 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................7.0v all inputs and outputs w.r.t. v ss ..........................................................................................................-0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied......................................................................................... .......-65c to +125c esd protection on all pins ............................................................................................................................... ....................... 4 kv table 1-1: dc characteristics figure 1-1: bus timing start/stop ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for an extended period of time may affect device reliability. dc characteristics v cc = +1.8v to +6.0v commercial (c): t a =0 c to +70 c industrial (i): t a =-40 c to +85 c automotive (e): t a =-40 c to +125 c parameter sym min max units conditions a0, a1, a2, scl and sda pins: high-level input voltage low-level input voltage hysteresis of schmitt trigger inputs low-level output voltage v ih v il v hys v ol .7 v cc ? .05 v cc ? ? .3 v cc ? .40 v v v v (note 1) i ol = 3.0 ma input leakage current i li ? 1 av in = .1v to v cc output leakage current i lo ? 1 av out = .1v to v cc pin capacitance (all inputs/outputs) c in , c out ?10pfv cc = 5.0v (note 1) t a = 25c, f clk = 1 mhz operating current i cc write i cc read ? ? 3 150 ma a v cc = 6.0v, scl = 400 khz v cc = 6.0v, scl = 400 khz standby current i ccs ?5 av cc = 5.0v, scl = sda = v cc a0, a1, a2 = v ss note 1: this parameter is periodically sampled and not 100% tested. t su : sta t hd : sta v hys t su : sto s tart s top scl sda
24aa65/24lc65/24c65 ds21073j-page 4 ? 2003 microchip technology inc. table 1-2: ac characteristics figure 1-2: bus timing data parameter symbol v cc = 1.8v-6.0v std. mode v cc = 4.5-6.0v fast mode units remarks min max min max clock frequency f clk ?100 ? 400khz clock high time t high 4000 ? 600 ? ns clock low time t low 4700 ? 1300 ? ns sda and scl rise time t r ? 1000 ? 300 ns (note 1) sda and scl fall time t f ? 300 ? 300 ns (note 1) start condition setup time t hd : sta 4000 ? 600 ? ns after this period the first clock pulse is generated start condition setup time t su : sta 4700 ? 600 ? ns only relevant for repeated start condition data input hold time t hd : dat 0? 0 ?ns data input setup time t su : dat 250 ? 100 ? ns stop condition setup time t su : sto 4000 ? 600 ? ns output valid from clock t aa ? 3500 ? 900 ns (note 2) bus free time t buf 4700 ? 1300 ? ns time the bus must be free before a new transmission can start output fall time from v ih min to v il max t of ? 250 20 + 0.1 c b 250 ns (note 1) , c b 100 pf input filter spike suppression (sda and scl pins) t sp 50 ? 50 ? ns (note 3) write cycle time t wr ? 5 ? 5 ms/page (note 4) endurance high endurance block rest of array 10m 1m ? ? 10m 1m ? ? cycles 25c, (note 5) note 1: not 100 percent tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise and spike suppression. this eliminates the need for a ti specification for standard operation. 4: the times shown are for a single page of 8 bytes. multiply by the number of pages loaded into the write cache for total time. 5: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be downloaded at www.microchip.com. scl sda in sda out t su : sta t sp t aa t f t low t high t hd : sta t hd : dat t su : dat t su : sto t buf t aa t r
? 2003 microchip technology inc. ds21073j-page 5 24aa65/24lc65/24c65 2.0 functional description the 24xx65 supports a bidirectional two-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. the bus must be controlled by a master device which generates the serial clock (scl), controls the bus access and generates the start and stop conditions, while the 24xx65 works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 3.0 bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device. 3.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24xx65) must leave the data line high to enable the master to generate the stop condition. figure 3-1: data transfer sequence on the serial bus note: the 24xx65 does not generate any acknowledge bits if an internal program- ming cycle is in progress. scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition
24aa65/24lc65/24c65 ds21073j-page 6 ? 2003 microchip technology inc. 3.6 device addressing a control byte is the first byte received following the start condition from the master device. the control byte consists of a four-bit control code, for the 24xx65 this is set as ? 1010 ? binary for read and write operations. the next three bits of the control byte are the device select bits (a2, a1, a0). they are used by the master device to select which of the eight devices are to be accessed. these bits are in effect the three most significant bits of the word address. the last bit of the control byte defines the operation to be performed. when set to a one a read operation is selected, when set to a zero a write operation is selected. the next two bytes received define the address of the first data byte (figure 4-1). because only a12..a0 are used, the upper three address bits must be zeros. the most significant bit of the most significant byte is transferred first. following the start condition, the 24xx65 monitors the sda bus checking the device type identifier being transmitted. upon receiving a ? 1010 ? code and appropriate device select bits, the slave device (24xx65) outputs an acknowledge signal on the sda line. depending upon the state of the r/w bit, the 24xx65 will select a read or write operation. figure 3-2: control byte allocation 4.0 write operation 4.1 byte write following the start condition from the master, the con- trol code (four bits), the device select (three bits), and the r/w bit which is a logic low, is placed onto the bus by the master transmitter. this indicates to the addressed slave receiver (24xx65) that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. there- fore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24xx65. the next byte is the least significant address byte. after receiving another acknowledge signal from the 24xx65, the master device will transmit the data word to be written into the addressed memory location. the 24xx65 acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time the 24xx65 will not generate acknowledge signals (figure 4-1). 4.2 page write the write control byte, word address and the first data byte are transmitted to the 24xx65 in the same way as in a byte write. but instead of generating a stop condition, the master transmits up to eight pages of eight data bytes each (64 bytes total), which are temporarily stored in the on-chip page cache of the 24xx65. they will be written from the cache into the eeprom array after the master has transmitted a stop condition. after the receipt of each word, the six lower order address pointer bits are internally incremented by one. the higher order seven bits of the word address remain constant. if the master should transmit more than eight bytes prior to generating the stop condition (writing across a page boundary), the address counter (lower three bits) will roll over and the pointer will be incremented to point to the next line in the cache. this can continue to occur up to eight times or until the cache is full, at which time a stop condition should be generated by the master. if a stop condition is not received, the cache pointer will roll over to the first line (byte 0) of the cache, and any further data received will overwrite previously captured data. the stop condition can be sent at any time during the transfer. as with the byte write operation, once the stop condition is received an internal write cycle will begin. the 64-byte cache will continue to capture data until a stop condition occurs or the operation is aborted (figure 4-2). operation control code device select r/w read 1010 device address 1 write 1010 device address 0 slave address 1 0 1 0 a2 a1 a0 r/w a start read/write
? 2003 microchip technology inc. ds21073j-page 7 24aa65/24lc65/24c65 figure 4-1: byte write figure 4-2: page write (for cache write, see figure 8-2) figure 4-3: current address read 000 bus activity master sda line bus activity s t a r t control byte word address (1) word address (0) data a c k a c k a c k a c k s t o p s p bus master sda line bus control byte word address (1) s t o p s t a r t a c k 0 a c k a c k activity activity : a c k a c k data n data n + 7 00 word address (0) p s sp bus activity master sda line bus activity s t a r t s t o p control byte data n a c k n o a c k
24aa65/24lc65/24c65 ds21073j-page 8 ? 2003 microchip technology inc. figure 4-4: random read figure 4-5: sequential read s da line bus control byte word address (1) s t o p s t a r t a c k a c k a c k activity a c k n o data n 000 word address (0) s t a r t control byte a c k p s s p bus activity master sda line bus activity s t o p control byte a c k n o a c k data n data n + 1 data n + 2 data n + x a c k a c k a c k
? 2003 microchip technology inc. ds21073j-page 9 24aa65/24lc65/24c65 5.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read and sequential read. 5.1 current address read the 24xx65 contains an address counter that main- tains the address of the last word accessed, internally incremented by one. therefore, if the previous access (either a read or write operation) was to address n (n is any legal address), the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to one, the 24xx65 issues an acknowledge and transmits the eight-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24xx65 discontinues transmission (figure 4-3). 5.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24xx65 as part of a write operation (r/w bit set to ? 0 ?). after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again, but with the r/w bit set to a one. the 24xx65 will then issue an acknowledge and transmit the eight-bit data word. the master will not acknowledge the transfer, but does generate a stop condition which causes the 24xx65 to discontinue transmission (figure 4-4). 5.3 sequential read sequential reads are initiated in the same way as a random read except that after the 24xx65 transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. this acknowledge directs the 24xx65 to transmit the next sequentially addressed 8-bit word (figure 4-5). following the final byte transmitted to the master, the master will not generate an acknowledge, but will generate a stop condition. to provide sequential reads the 24xx65 contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 5.4 contiguous addressing across multiple devices the device select bits a2, a1, a0 can be used to expand the contiguous address space for up to 512k bits by adding up to eight 24xx65's on the same bus. in this case, software can use a0 of the control byte as address bit a13, a1 as address bit a14 and a2 as address bit a15. 5.5 noise protection the scl and sda inputs have filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. all i/o lines incorporate schmitt triggers for 400 khz (fast mode) compatibility. 5.6 high endurance block the location of the high endurance block within the memory map is programmed by setting the leading bit 7 (s/he ) of the configuration byte to ? 0 ?. the upper bits of the address loaded in this command will determine which 4k block within the memory map will be set to high endurance. this block will be capable of 10,000,000 erase/write cycles typical (figure 8-1). the high endurance block will retain its value as the high endurance block even if it resides within the security block range. the high endurance setting always takes precedence to the security setting. note: the high endurance block cannot be changed after the security option has been set with a length greater than zero. if the h.e. block is not programmed by the user, the default location is the highest block of memory which starts at location 0x1e00 and ends at 0x1fff.
24aa65/24lc65/24c65 ds21073j-page 10 ? 2003 microchip technology inc. 5.7 security options the 24xx65 has a sophisticated mechanism for write protecting portions of the array. this write-protect function is programmable and allows the user to protect 0-15 contiguous 4k blocks. the user sets the security option by sending to the device the starting block number for the protected region and the number of blocks to be protected. all parts will come from the factory in the default configuration with the starting block number set to 15 and the number of protected blocks set to zero. the security option can be set only once with a length greater than zero. to invoke the security option, a write command is sent to the device with the leading bit (bit 7) of the first address byte set to a ? 1 ? (figure 8-1). bits 1-4 of the first address byte define the starting block number for the protected region. for example, if the starting block number is to be set to 5, the first address byte would be 1xx0101x. bits 0, 5 and 6 of the first address byte are disregarded by the device and can be either high or low. the device will acknowledge after the first address byte. a byte of don?t care bits is then sent by the master, with the device acknowledging afterwards. the third byte sent to the device has bit 7 (s/he) set high and bit 6 (r) set low. bits 4 and 5 are don?t cares and bits 0-3 define the number of blocks to be write-protected. for example, if three blocks are to be protected, the third byte would be 10xx0011. after the third byte is sent to the device, it will acknowledge and a stop bit is then sent by the mas- ter to complete the command. if one of the security blocks coincides with the high endurance block, the high endurance setting will take precedence. also, if the range of the security blocks encompass the high endurance block when the secu- rity option is set, the security block range will be set accordingly, but the high endurance block will continue to retain the high endurance setting. as a result, the memory blocks preceding the high endurance block will be set as secure sections. during a normal write sequence, if an attempt is made to write to a protected address, no data will be written and the device will not report an error or abort the command. if a write command is attempted across a secure boundary, unprotected addresses will be written and protected addresses will not. 5.8 security configuration read the status of the secure portion of memory can be read by using the same technique as programming this option except the read bit (bit 6) of the configuration byte is set to a one. after the configuration byte is sent, the device will acknowledge and then send two bytes of data to the master just as in a normal read sequence. the master must acknowledge the first byte and not acknowledge the second, and then send a stop bit to end the sequence. the upper four bits of both of these bytes will always be read as ?1?s. the lower four bits of the first byte contains the starting secure block. the lower four bits of the second byte contains the number of secure blocks. the default starting secure block is fifteen and the default number of secure blocks is zero (figure 8-1). 6.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 6-1 for flow diagram. figure 6-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes
? 2003 microchip technology inc. ds21073j-page 11 24aa65/24lc65/24c65 7.0 page cache and array mapping the cache is a 64-byte (8 pages x 8 bytes) fifo buffer. the cache allows the loading of up to 64 bytes of data before the write cycle is actually begun, effectively providing a 64-byte burst write at the maximum bus rate. whenever a write command is initiated, the cache starts loading and will continue to load until a stop bit is received to start the internal write cycle. the total length of the write cycle will depend on how many pages are loaded into the cache before the stop bit is given. maximum cycle time for each page is 5 ms. even if a page is only partially loaded, it will still require the same cycle time as a full page. if more than 64 bytes of data are loaded before the stop bit is given, the address pointer will ?wrap around? to the beginning of cache page 0 and existing bytes in the cache will be overwritten. the device will not respond to any commands while the write cycle is in progress. 7.1 cache write starting at a page boundary if a write command begins at a page boundary (address bits a2, a1 and a0 are zero), then all data loaded into the cache will be written to the array in sequential addresses. this includes writing across a 4k block boundary. in the example shown below, (figure 8-2) a write command is initiated starting at byte 0 of page 3 with a fully loaded cache (64 bytes). the first byte in the cache is written to byte 0 of page 3 (of the array), with the remaining pages in the cache written to sequential pages in the array. a write cycle is executed after each page is written. since the write begins at page 3 and 8 pages are loaded into the cache, the last 3 pages of the cache are written to the next row in the array. 7.2 cache write starting at a non-page boundary when a write command is initiated that does not begin at a page boundary (i.e., address bits a2, a1 and a0 are not all zero), it is important to note how the data is loaded into the cache, and how the data in the cache is written to the array. when a write command begins, the first byte loaded into the cache is always loaded into page 0. the byte within page 0 of the cache where the load begins is determined by the three least significant address bits (a2, a1, a0) that were sent as part of the write command. if the write command does not start at byte 0 of a page and the cache is fully loaded, then the last byte(s) loaded into the cache will roll around to page 0 of the cache and fill the remaining empty bytes. if more than 64 bytes of data are loaded into the cache, data already loaded will be overwritten. in the example shown in figure 8-3, a write command has been initiated starting at byte 2 of page 3 in the array with a fully loaded cache of 64 bytes. since the cache started loading at byte 2, the last two bytes loaded into the cache will ?roll over' and be loaded into the first two bytes of page 0 (of the cache). when the stop bit is sent, page 0 of the cache is written to page 3 of the array. the remaining pages in the cache are then loaded sequentially to the array. a write cycle is executed after each page is written. if a partially loaded page in the cache remains when the stop bit is sent, only the bytes that have been loaded will be written to the array. 7.3 power management the design incorporates a power standby mode when not in use and automatically powers off after the normal termination of any operation when a stop bit is received and all internal functions are complete. this includes any error conditions (i.e., not receiving an acknowl- edge or stop condition per the two-wire bus specifica- tion). the device also incorporates v dd monitor circuitry to prevent inadvertent writes (data corruption) during low voltage conditions. the v dd monitor circuitry is powered off when the device is in standby mode in order to further reduce power consumption. 8.0 pin descriptions 8.1 a0, a1, a2 chip address inputs the a0..a2 inputs are used by the 24xx65 for multiple device operation and conform to the two-wire bus standard. the levels applied to these pins define the address block occupied by the device in the address map. a particular device is selected by transmitting the corresponding bits (a2, a1, a0) in the control byte (figure 3-2 and figure 8-1). 8.2 sda serial address/data input/ output this is a bidirectional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal, therefore the sda bus requires a pull-up resistor to v cc (typical 10 k ? for 100 khz, 2 k ? for 400 khz). for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 8.3 scl serial clock this input is used to synchronize the data transfer from and to the device.
24aa65/24lc65/24c65 ds21073j-page 12 ? 2003 microchip technology inc. figure 8-1: control sequence bit assignments a 1 control byte a 2 a 0 r/w 0 1 0 1 a 10 address byte 1 a 11 a 9 a 8 0 0 s a 7 a 0 address byte 0 slave address device select bits a 12 b 2 configuration byte b 3 b 1 b 0 x r x block count s/he a 1 a 2 a 0 0 1 0 1 x xxx x x 1 x starting block number s t a r t 0 x xxx x x x x a c k x xxx x 1 1 x a c k b 2 b 3 b 1 b 0 1 1 1 1 n 2 n 3 n 1 n 0 1 1 1 1 number of blocks to protect s t o p a c k no ack data from device acknowledge from master data from device acknowledges from device a 1 a 2 a 0 0 1 0 1 b 1 b 2 b 0 x x x 1 b 3 s t a r t 0 x xxx x x x x n 2 n 3 n 1 n 0 x 0 1 x a c k s t o p acknowledges from device a 1 a 2 a 0 a c k 0 1 0 1 x xxx x x 1 x high endurance block number s t a r t 0 x xxx x x x x a c k x xxx x 1 0 x a c k b 2 b 3 b 1 b 0 1 1 1 1 s t o p a c k no ack data from device acknowledges from device a 1 a 2 a 0 a c k 0 1 0 1 b 1 b 2 b 0 x x x 1 b 3 s t a r t 0 x xxx x x x x a c k 0 000 x 0 0 x a c k s t o p a c k acknowledges from device starting block number number of blocks to protect r s/he r s/he r s/he r s/he s ecurity read s ecurity write h igh endurance block read h igh endurance block write a c k a c k a c k a c k a c k high endurance block number
? 2003 microchip technology inc. ds21073j-page 13 24aa65/24lc65/24c65 figure 8-2: cache write to the array starting at a page boundary figure 8-3: cache write to the array starting at a non-page boundary 1 write command initiated at byte 0 of page 3 in the array; first data byte is loaded into the cache byte 0. 2 64 bytes of data are loaded into cache. 3 write from cache into array initiated by stop bit. page 0 of cache written to page 3 of array. write cycle is executed after every page is written. 4 remaining pages in cache are written to sequential pages in array. cache byte 0 cache byte 1 cache byte 7 cache page 1 bytes 8-15 page 0 cache page 2 bytes 16-23 cache page 7 bytes 56-63 page 1 page 2 byte 7 page 4 page 7 page 3 cache page 0 last page in cache written to page 2 in next row. 5 array row n array row n + 1 page 0 page 1 page 2 byte 0 byte 1 page 4 page 7 1 write command initiated; 64 bytes of data loaded into cache starting at byte 2 of page 0. 2 last 2 bytes loaded 'roll over' to beginning. 3 l ast 2 bytes l oaded into p age 0 of cache. 4 write from cache into array initiated by stop bit. page 0 of cache written to page 3 of array. write cycle is executed after every page is written. cache byte 1 cache byte 2 cache byte 7 cache page 1 bytes 8-15 page 0 cache page 2 bytes 16-23 cache page 7 bytes 56-63 page 1 page 2 page 4 page 7 page 3 remaining bytes in cache are written sequentially to array. 5 array row n array row n + 1 cache byte 0 last 3 pages in cache written to next row in array. 6 page 1 page 2 byte 0 byte 2 byte 1 page 4 page 7 byte 7 byte 3 byte 4 page 0
24aa65/24lc65/24c65 ds21073j-page 14 ? 2003 microchip technology inc. 9.0 packaging information 9.1 package marking information xxxxxxxx t/xxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (208 mil) example: 24lc65 0110017 i/sm 24lc65 i/p017 0310 xxxxxxxx yywwnnn t/xxxxxx legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code t temperature grade (blank = commercial, i = industrial, e = automotive) note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard picmicro device marking consists of microchip part number, year code, week code, and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price.
? 2003 microchip technology inc. ds21073j-page 15 24aa65/24lc65/24c65 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
24aa65/24lc65/24c65 ds21073j-page 16 ? 2003 microchip technology inc. 8-lead plastic small outline (sm) ? medium, 208 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.43 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.64 0.51 .030 .025 .020 l foot length 5.33 5.21 5.13 .210 .205 .202 d overall length 5.38 5.28 5.11 .212 .208 .201 e1 molded package width 8.26 7.95 7.62 .325 .313 .300 e overall width 0.25 0.13 0.05 .010 .005 .002 a1 standoff 1.98 .078 a2 molded package thickness 2.03 .080 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 a a1 l c 2 1 d n p b e e1 .070 .075 .069 .074 1.78 1.75 1.97 1.88 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. drawing no. c04-056 significant characteristic
? 2003 microchip technology inc. ds21073j-page 17 24aa65/24lc65/24c65 appendix a: revision history revision j corrections to section 1.0, electrical characteristics.
24aa65/24lc65/24c65 ds21073j-page 18 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds21073j-page 19 24aa65/24lc65/24c65 on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
24aa65/24lc65/24c65 ds21073j-page 20 ? 2003 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21073j 24aa65/24lc65/24c65 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2003 microchip technology inc. ds21073j-page 21 24aa65/24lc65/24c65 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . sales and support part no. x /xx xxx pattern package temperature range device device 24aa65 - 64k i 2 c 1.8v serial eeprom (100 khz) 24aa65t - 64k i 2 c 1.8v serial eeprom (100 khz) 24lc65 - 64k i 2 c serial eeprom (100 khz/400 khz) 24lc65t - 64k i 2 c serial eeprom (tape and reel) 24c65 - 64k i 2 c 4.5v serial eeprom (400 khz) 24c65t - 64k i 2 c 4.5v serial eeprom (tape and reel) temperature range blank = 0 c to +70 c i= -40 c to +85 c e= -40 c to +125 c package p = plastic dip (300 mil body) sm = plastic soic (207 mil body, eiaj standard) examples: a) 24lc65t-i/sm: 64 kbit smart serial, tape and reel, 207 mil soic package, industrial temperature, 2.5v b) 24lc65-i/p: 64 kbit smart serial, industrial temperature, pdip package, 2.5v c) 24aa65t-/sm: 64 kbit smart serial, tape and reel, 207 mil soic package, commercial temperature, 1.8v d) 24c65-e/p: 64 kbit smart serial, automotive temperature, pdip, 5v data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
24aa65/24lc65/24c65 ds21073j-page 22 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds21073j-page 23 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microc hip?s products as critical com- ponents in life support systems is not authorized except with express written approval by mi crochip. no licenses are con- veyed, implicitly or otherwis e, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of micr ochip technology incorporated in the u.s.a. application maestro, dspicdem, dspicdem.net, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smar ttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned he rein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are comm itted to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
ds21073j-page 24 ? 2003 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com atlanta 3780 mansell road, suite 130 alpharetta, ga 30022 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, in 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 phoenix 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-4338 san jose 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu rm. 2401-2402, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - hong kong sar unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen rm. 1812, 18/f, building a, united plaza no. 5022 binhe road, futian district shenzhen 518033, china tel: 86-755-82901380 fax: 86-755-8295-1393 china - shunde room 401, hongjian building no. 2 fengxiangnan road, ronggui town shunde city, guangdong 528303, china tel: 86-765-8395507 fax: 86-765-8395571 china - qingdao rm. b505a, fullhope plaza, no. 12 hong kong central rd. qingdao 266071, china tel: 86-532-5027355 fax: 86-532-5027205 india divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 taiwan kaohsiung branch 30f - 1 no. 8 min chuan 2nd road kaohsiung 806, taiwan tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan taiwan branch 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe austria durisolstrasse 2 a-4600 wels austria tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45-4420-9895 fax: 45-4420-9910 france parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany steinheilstrasse 10 d-85737 ismaning, germany tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy via quasimodo, 12 20025 legnano (mi) milan, italy tel: 39-0331-742611 fax: 39-0331-466781 netherlands p. a. de biesbosch 14 nl-5152 sc drunen, netherlands tel: 31-416-690399 fax: 31-416-690340 united kingdom 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-118-921-5869 fax: 44-118-921-5820 07/28/03 w orldwide s ales and s ervice

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